parallel hardware architecture的意思|示意
并行硬件架构
parallel hardware architecture的网络常见释义
并行结构 ...;并行结构;最佳组合 [gap=629]Keyword: ECC; point multiplication; coordinate conversion; parallel hardware architecture; best combination ...
parallel hardware architecture相关短语
1、 multi-algorithm parallel processor hardware architecture 多算法并行处理
parallel hardware architecture相关例句
The algorithm has lower complexities and good parallel architecture, and is suitable for the high-speed low-power hardware realization and real-time processing.
该算法复杂度低,并行性好,支持高速低功耗硬件实现,能实现对空间数据的实时处理,在空间探测领域具有良好的应用前景。
This thesis achieves the following three innovative results: 1 the thesis presents a new parallel array 2-d discrete wavelet transform DWT hardware architecture based on lifting schemes.
以下是本文的三个创新性成果:1设计了一种并行阵列式二维离散小波变换DWT提升格式的硬件结构。
Neural network possesses many of advantages : simple structure, easy implementation in hardware, the basic parallel computational architecture, etc.
人工神经网络的特点是:结构简单、能够大规模并行、容易用硬件实现等。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程,提出了双上下文窗口位并行的EBCOT系数位建模方法,详细说明了使用该算法的系数位建模系统的硬件结构。
The EBCOT design USES parallel processing and dynamic memory control (DMC) architecture, which greatly speeds up the coding process and achieves higher hardware utilization.
EBCOT采用的并行运算和动态内存控制(DMC)结构,在保证编码速度的前提下,最大限度减小了片内小波系数缓存量和访问频率。
In this paper, a hardware-oriented, full pass-parallel coding architecture is presented, based on only one scanning window. This architecture is verified on FPGA.
该文设计出一种适用于硬件实现的单窗口全通道并行编码结构,目前已通过FPGA验证。