gate-level logic simulation的意思|示意
门级逻辑模拟
gate-level logic simulation的网络常见释义
门级逻辑模拟 ... gate level logic simulation 门级逻辑模拟 gate-level logic simulation 门级逻辑模拟 hierarchical logic high level 分级逻辑高电平 ...
gate-level logic simulation相关短语
1、 gate level logic simulation 门级逻辑模拟 ; 闸位准逻辑仿真
2、 gate footstep level logic simulation 门级逻辑模拟
gate-level logic simulation相关例句
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。