Clock Conditioning Circuit的意思|示意
时钟调节电路
Clock Conditioning Circuit的网络常见释义
个时脉调节电路 ...文化 Asia-info hold)功能 3个12位元sigma-delta DAC，有500Ksps的更新速率 5个时脉调节电路(Clock Conditioning Circuit, CCC)及2个内建类比锁相回路(PLL)，具有相位迁移，乘法/除法及延时功能，输入频率可从1.5到350MH..
Clock Conditioning Circuit相关例句
The data acquisition system consists of the signal conditioning circuit, DSK interfacing circuit, RS-485 communication interfacing circuit, system clock circuit, the power circuit, and so on.
数据采集系统包括信号调理电路、DSK接口电路、RS - 485通信接口电路、系统时钟电路及电源电路等。